The subject matter relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a bit line sense amplifier with a structure for overdriving. More specifically, the present invention relates to a circuit that can stabilize a voltage applied to a normal driving voltage terminal in an overdriving operation and a subsequent normal driving operation.
As the line width and cell size in semiconductor memory designs have been gradually scaled down, semiconductor memory devices have been designed to operate with a lower power supply voltage. Thus, there is a demand for a design technique providing the desired performance in a low-voltage environment.
In most semiconductor memory devices, there is an integrated internal voltage generator for receiving an external power supply voltage (VDD) to generate an internal voltage. Therefore, a semiconductor memory device generates a voltage for operating an internal circuit via an internal voltage generator for itself.
A memory device such as a dynamic random access memory (DRAM), which utilizes a bit line sense amplifier, uses a normal driving voltage (generally, a core voltage (VCORE)) to detect a cell data.
When a word line selected by a row address is enabled, data of a plurality of memory cells connected to the selected word line are transferred to bit lines, and corresponding bit line sense amplifiers each sense and amplify a voltage difference of a bit line pair.
Generally, several thousands of bit line sense amplifiers are operated at the same time. Thus, a large amount of current is consumed on a normal driving voltage terminal at once, which is used in driving a pull-up voltage line of the bit line sense amplifiers, called RTO.
However, in the trend of lower operating voltage, there are limitations for amplifying the data of a large number of memory cells at once in a short period of time by using the normal driving voltage.
To solve this problem, a bit line sense amplifier overdriving scheme was adopted. In an initial operation of the bit line sense amplifier, that is, immediately after a charge sharing between a memory cell and a bit line pair, a voltage line RTO of the bit line sense amplifier is driven by an overdriving voltage (generally, a power supply voltage (VDD)) higher than a normal driving voltage (generally, a core voltage (VCORE)) for a predetermined time.
FIG. 1 is a block diagram of a conventional semiconductor memory device having a bit line sense amplifier with a structure for an overdriving.
Referring to FIG. 1, the conventional semiconductor memory device includes a bit line sense amplifier 100, a voltage line driver 120, a normal driving voltage charge driver 140, and a normal driving voltage discharge driver 160. The bit line sense amplifier 100 senses and amplifies a data applied to bit lines. The voltage line driver 120 drives voltage lines RTO and SB of the bit line sense amplifier 100 to a normal driving voltage or an overdriving voltage. The normal driving voltage charge driver 140 pulls up a normal driving voltage terminal when a voltage level of the normal driving voltage terminal is lower than a first target normal driving voltage level. The normal driving voltage discharge driver 160 pulls down a normal driving voltage terminal when the voltage level of the normal driving voltage terminal is higher than a second target normal driving voltage level.
The voltage line driver 120 includes an overdriving unit 122 and a normal driving unit 124. The overdriving unit 122 drives the voltage lines RTO and SB of the bit line sense amplifier 100 to the overdriving voltage in the overdriving period. The normal driving unit 124 drives the voltage lines RTO and SB of the bit line sense amplifier 100 to the normal driving voltage in the normal driving period.
An operation of the conventional semiconductor memory device will be described below.
The voltage line driver 120 drives the voltage lines RTO and SB of the bit line sense amplifier 100 to the overdriving voltage in the overdriving period in response to an overdriving signal SAOVDP. Then, the voltage line driver 120 drives the voltage lines RTO and SB of the bit line sense amplifier 100 to the normal driving voltage in the normal driving period.
In response to a charge enable signal CEP, the normal driving voltage charge driver 140 pulls up the normal driving voltage terminal when the voltage levels of the voltage lines RTO and SB are lower than the first target normal driving voltage level in the overdriving period and the normal driving period with respect to a reference voltage VREF1 corresponding to the first target normal driving voltage level.
In response to a discharge enable signal DCEP, the normal driving voltage discharge driver 160 pulls down the normal driving voltage terminal when the voltage levels of the voltage lines RTO and SB are higher than the second target normal driving voltage level in the overdriving period and the normal driving period with respect to a second reference voltage VREF2 corresponding to the second target normal driving voltage level.
The normal driving voltage charge driver 140 is designed to maintain the normal driving voltage terminal to a voltage level higher than the first target normal driving voltage level. The voltage level at the normal driving voltage terminal may be decreased by the use of the normal driving voltage at the operation of the semiconductor memory device or a natural discharge. Therefore, the operation of the normal driving voltage charge driver is determined by the voltage level of the normal driving voltage terminal in such a state that the charge enable signal CEP is activated, regardless of the operation of the semiconductor memory device.
Like the normal driving voltage charge driver 140, the normal driving voltage discharge driver 160 is designed to maintain the normal driving voltage terminal to a voltage level lower than the second target normal driving voltage level. Therefore, basically in such a state that the discharge enable signal DCEP is activated, it is determined whether the normal driving voltage discharge driver operates or not by the voltage level of the normal driving voltage terminal.
However, in a specific operation such as the overdriving operation, if a discharge operation is performed because the voltage level of the normal driving voltage terminal is higher than the second target normal driving voltage level, a normal overdriving operation cannot be achieved.
Therefore, in the case of specific operations such as the overdriving operation, the discharge enable signal DCEP is activated for a predefined time with a predefined timing after an overdriving operation begins.
However, in the case of the overdriving voltage, power supply voltage VDD is used, which is provided from outside of the semiconductor memory device. Due to environmental factors that affect the overdriving voltage, it may be higher or lower than a predefined level when supplied to the semiconductor memory device. That is, since the overdriving voltage is provided from the outside of the semiconductor memory device, its voltage level may fluctuate.
In the overdriving operation using an overdriving voltage lower or higher than the predefined level and the subsequent normal driving operation, the corresponding level of the normal driving voltage terminal may vary as described below.
FIG. 2 is a signal timing diagram illustrating voltages applied to the normal driving voltage terminal in the overdriving operation and the subsequent normal driving operation of a conventional semiconductor memory device.
It can be seen from FIG. 2 that the voltage applied to the normal driving voltage terminal varies according to the overdriving voltage level in the overdriving operation and the subsequent normal driving operation.
In a case {circle around (2)} where the predefined level (normal VDD) is inputted as the overdriving voltage level, the voltage level of the normal driving voltage terminal, which is increased in the overdriving operation, returns to the level (normal VCORE) defined prior to the overdriving operation due to the operation of the normal driving voltage discharge driver 160.
However, in a case {circle around (1)} where the supplied overdriving voltage level is higher than the predefined level, that is, the overdriving voltage level is a high VDD, the voltage level of the normal driving voltage terminal, which increases more than when a normal VDD is supplied during the overdriving operation, does not return to the normal VCORE level from prior to the overdriving operation, but remains at a higher level, in spite of the operation of the normal driving voltage discharge driver 160.
Further, in a case {circle around (3)} where the supplied overdriving voltage level is lower than the predefined level, that is, the overdriving voltage level is a low VDD, the voltage level of the normal driving voltage terminal, which increases less than when a normal VDD is supplied during the overdriving operation, falls below the normal VCORE from prior to the overdriving operation due to the operation of the normal driving discharge driver 160.
As described above, when a voltage level higher or lower than a normal VDD is supplied as the overdriving voltage level, the voltage level of the normal driving voltage terminal does not return to the normal VCORE from prior to an overdriving operation, in spite of the normal operation of the normal driving discharge driver 160.
When the voltage does not return to the normal VCORE level after the overdriving operation, and is directly applied to the voltage lines RTO and SB of the bit line sense amplifier 100 in the normal driving operation, the bit line sense amplifier 100 may perform an erroneous operation, resulting in defective operation of the semiconductor memory device.